Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
Description of the Related Art
In recent years, the miniaturization of semiconductor devices has made progress, thus resulting in a decrease in the equivalent oxide thickness (EOT) of a gate insulating film. Accordingly, a major increase in leakage current due to the decrease in the EOT has become problematic in a gate insulating film based on a silicon oxynitride film and a silicon oxide film, and a gate electrode structure made from polysilicon which have been used. Hence, an HKMG transistor is a focus of attention as a new technique to solve such a problem. The HKMG transistor is a transistor which comprises a gate insulating film including a high-dielectric insulating film higher in dielectric constant than oxide silicon, and a gate electrode including a metal layer. In the HKMG transistor, the high-dielectric insulating film is used for the gate insulating film, and therefore, gate leakage currents can be suppressed by increasing the physical thickness of the gate insulating film while decreasing the EOT. In addition, use of the gate electrode including the metal layer can improve the operating characteristics of the transistor.
JP2006-24594A and JP2007-329237A disclose the HKMG transistor.
A related method for manufacturing the HKMG transistor will be described with reference to FIGS. 26 to 28.
First, as illustrated in FIG. 26A, there is prepared semiconductor substrate 1 in which P well 3 and N well 4 are disposed through isolation region 2. A first laminated film including silicon oxide film 5a, first high-dielectric insulating film 6a, first metal film 7a, and impurity-containing polysilicon film 8a is formed on P well 3, and a second laminated film including silicon oxide film 5b, first high-dielectric insulating film 6b, second high-dielectric insulating film 6c, first metal film 7b, and impurity-containing polysilicon film 8b is formed on N well 4. At this time, one end 10a of the first laminated film and one end 10b of the second laminated film are positioned on isolation region 2. In addition, trench portion 13 is formed of a side surface of end 10a, a side surface of end 10b, and a front surface of isolation region 2.
As illustrated in FIG. 26B, impurity-containing polysilicon film 11 and second metal film 12 are formed so as to extend in first direction 60 indicated above semiconductor substrate 1 from the space on P well 3 through the space on isolation region 2 to the space on N well 4. At this time, trench portion 13 cannot be completely filled with polysilicon film 11 and second metal film 12 since the aspect ratio of trench portion 13 is high, and therefore, seam 14 arises within trench portion 13. Under this condition, silicon nitride film 15 for use as a mask is formed on semiconductor substrate 1 by a plasma CVD method, so as to cover second metal film 12. At this time, silicon nitride film 15 fails to completely fill seam 14 since the plasma CVD method is inferior in coverage (step coverage), and therefore, seam 14 remains within silicon nitride film 15.
As illustrated in FIG. 27A, silicon nitride film 15 is patterned to form hard mask 15. The first and second laminated films and portions of polysilicon film 11 and second metal film 12 on isolation region 2 are patterned by etching using hard mask 15. Consequently, first and second gate electrodes 17a and 17b are formed on P well 3 and N well 4, respectively, and wiring 20 is formed on isolation region 2. LDD regions 19a of the N conductivity type are formed within P well 3, and LDD regions 19b of the P conductivity type are formed within N well 4. Offset spacers 26a are formed on the side surfaces of first and second gate electrodes 17a and 17b and wiring 20. Thereafter, first source and drain 21a of the N conductivity type are formed within P well 3, and second source and drain 21b of the P conductivity type are formed within N well 4. SOD film 22 is formed on semiconductor substrate 1, and then CMP treatment or etched back of SOD film 22 is performed to expose hard mask 15. At this time, seam 14 remains as is within wiring 20, and second metal film 12 is exposed on the bottom of seam 14.
As illustrated in FIG. 27B, a contact hole to expose therein first source and drain 21a is formed within SOD film 22. Thereafter, an electrically conductive material is formed so as to fill the contact hole, thereby forming contact plug 24 therein. At this time, seam 14 within wiring 20 is also filled with the electrically conductive material to form conductive part 20a. 
FIG. 28A is a plan view, and FIG. 28B represents a cross-sectional view taken along the A-A′ direction of FIG. 28A. As illustrated in FIGS. 28A and 28B, wirings 25a and 25b are formed on SOD film 22, so as to contact with hard mask 15. Here, wirings 25a and 25b are electrically connected to conductive part 20a since conductive part 20a has been formed in the process of FIG. 27B. As a result, the related method has been problematic in that wirings 25a and 25b short-circuit to each other through conductive part 20a. 